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Lattice Semiconductor
PCI Express User’s Guide
txtlpu_rdy – If the core is ready to service the request it asserts this output signal so that the user inter-
face logic can start the transaction.
txtlpu_st – User ia nterface logic asserts this input signal to indicate the start of TLP and simultaneously
loads the ?rst DWORD of the TLP into the txtlpu_data bus. This signal should be active for only one clock
period. All remaining parts of the TLP are loaded into the core in subsequent clocks, 32 bits per clock. Each
DWORD of data is strobed in by the core at every positive edge of the div2_pclk clock.
txtlpu_end – User interface logic asserts this signal along with the last DWORD of the TLP in the
txtlpu_data bus. This is to indicate the end of Tx transaction. This signal should be active for only one
clock period.
txtlpu_nlfy – If the current Tx TLP is to be a nulli?ed TLP the user interface logic asserts this to indicate
the end of the nulli?ed TLP. This signal should be active for only one clock period.
The user interface logic can hold the txtlpu_req asserted to continue to transmit TLPs as long as txtlpu_rdy
is asserted the txtlpu_st , txtlpu_end and txtlpu_nlfy signals are required to be asserted at the appropri-
ate time for each TLP as explained above.
The core expects that the request from the user logic is always to transmit a full TLP. So the core will respond with
txtlpu_rdy only if it has enough memory in the retry buffer to cater a TLP even with maximum payload.
The data transfer from the user logic and the core should be continuous without any break between the start of a
TLP (as indicated by txtlpu_st ) and the end of a TLP (as indicated by txtlpu_end ) hence txtlpu_req
should be held asserted till the end of a TLP. If the txtplu_req is deasserted by the user logic before the end of a
TLP the core behavior will be unknown and the user logic should start a TLP afresh.
Based on the packet type selected by the user logic in the input signal pkt_type the core loads the corresponding
Credit Available information in the output signal crdt_avail . In the above ?gure p_c, NP_c and cpl_c are the cor-
responding Credit Available values for the packet types p, NP and cpl. For more information about Credit Available
Calculation please refer to the appropriate section under Functional Description.
Figure 5 shows the signal status for Transmit User Interface.
Register Description
PCI Express con?guration space is not implemented in this core. But the core checks all TLPs related to the con?g-
uration access and appropriate action, as speci?ed, is carried out in case of errors. It is left to the user logic to
implement the necessary PCI Express registers as part of the design. All status and error signals are provided at
the user interface to connect them to proper registers in the user logic.
User Con?gurable Parameters
The PCI Express core has all the three layers of the Endpoint device that is implemented in one con?guration.
Therefore there are no other con?gurations of this core.
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相关PDF资料
PCM18XH2
PROCESSOR MODULE MPLAB-ICE 2000
PCM18XN0
PROCESSOR MODULE FOR ICE2000
PDA-B-24-615-E-2B1-1-C
CIRCUIT BREAKER MAG 1P 15A
PFMF.260.2
PFMF PTC FUSE SMT 2.6A 1812
PFNF.200.2
PFNF PTC FUSE SMT 2A 1206
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